Processor Whispers - About War and Peace

by Andreas Stiller

The H is proud to present Andreas Stiller's Processor Whispers as a regular new feature of The H. Processors are, quite literallly, core to both open source software and security, and we hope this new feature will keep readers abreast of current and future developments.

Intel and AMD have come to an arrangement and now AMD can cheerfully present new roadmaps without worrying about pesky patents. Meanwhile, problems arise between Microsoft and Intel; the Redmonders were actually planning to advise against the application of Nehalem Xeons under Windows Server 2008 R2.

The game has changed: the companies, Intel and AMD, have amicably settled all their legal disputes. Worldwide, AMD drops all lawsuits for unfair competitive conduct against Intel and withdraws all appeals. In exchange, AMD receives a compensation of $1.25 billion in cash and – even more important from AMD’s perspective – Intel’s promise to comply with a negotiated code of fair business practices.

AMD wants to give hard, but fair competition to its new friend Intel – in the form of two new architectures: the Bobcat, designed to challenge the Atom, and the Bulldozer, a kind of hybrid of hyper-threading and dual-core. AMD’s spin-off manufacturing arm Globalfoundries can now act as an autonomous company without being bound to a formal AMD majority via artificial constructions – as it had been until now by a stipulation in the patent exchange agreement from 2001. Intel assigns the rights to produce x86 chips to Globalfoundries through a separate contract. Additionally, AMD can also charge other third-party manufacturers with the production of processors.

Balance

The cross-licensing agreement between Intel and AMD will be extended by five years – something profitable for both sides, as AMD could do with innovations like the up-coming vector extension AVX and Intel needs AMD’s 64-bit patents. The agreement covers the complete patent portfolio, including ATI’s graphic patents, which now are at Intel’s disposal. Until now, AMD had been paying licensing fees of undisclosed amounts to Intel on a quarterly basis; if that will still be the case in the future, has not been conveyed.

Meanwhile, Intel emphasizes that it is not aware of being guilty of anything, that its conduct has always been correct and that all it did was offer normal discounts and rebates. According to Intel, the only motivation behind its concessions to AMD was to end the legal dispute that already included 200 million pages of documents and would otherwise probably have taken many years to come to an end, and to stem the exploding court and lawyer fees. However, the legal proceedings in the EU and in New York, and now also cases filed by shareholders for monopoly abuse, will continue. Maybe the agreement was facilitated by the recent departures of the two hardliners Pat Gelsinger, on one side, and Hector Ruiz, on the other. Now, the two rivals’ relationship will be a “balance of fierce and fair competition”, says AMD.

In the face of the positive turn AMD could cheerfully present new roadmaps and reveal some details on the processor architectures Bulldozer and Bobcat – due 2011 – even before the agreement had been officially announced. In the end, the Bulldozer is supposed to adopt Intel’s AVX extension while AMD’s own, already released alternative SSE5 will most likely be abandoned. For those who don’t know already: the Bulldozer is a concept in which each core consists of two integer sub-cores that have their own L1 caches and they share a common L2 cache and common L3 cache with a single floating-point sub-core without L1 cache. The L1 caches are supposed to be rather small, the talk is of 8 KB. Like with Intel’s Nehalem, the two integer sub-cores work with 4 parallel pipelines, the floating-point part occupies two of the pipelines, each one of which is capable of 128-bit FMAC operations (multiplication and addition in one step). The 128 bits hint that the 256-bit wide AVX will probably at first be split in two, like, for example, the Barcelona processor formerly split up the 128-bit SSE in two 64-bit operations. At least the Bulldozer does feature FMAC – Intel’s first AVX processor, the Sandy Bridge, will probably not include it.

Core Business

In order to make current operating systems compatible with AMD’s core architecture, the FPU somehow has to operate with a kind of hyper-threading, so that the operating system – and its users – can accept the whole design as a full-fledged duo-core. The 8-core processor Zambesi, planned for high-end desktop computers and slated for 2011, will probably have four of those duo-cores. In the context of “Fusion”, AMD also plans to squeeze a graphics processor on the chip, which is why it is called an Accelerated Processing Unit (APU) in AMD jargon.

In the form of a normal CPU, the Bulldozer architecture might already make an appearance toward the end of 2010, as the G34-Opteron Interlagos with 12 to 16 cores or the C32-Opteron Valencia with 6 to 8 cores, manufactured by Globalfoundries on silicon-on-insulator (SOI) wafers in the 32-nm process. The G34 version is aimed at servers with four processor sockets and will feature four DDR3 memory channels and four HyperTransport 3.0 links per CPU. The C32 is aimed at server boards with one or two sockets; each CPU is planned to have two DDR3 memory channels. The matching server chip-sets are already being sold, but only on LGA1207 boards. By the way, they also support AMD-Vi, the I/O virtualisation (IOMMU 1.2) announced in 2006.

As competitor to the Atom, the Bobcat is supposed to roll out – as a very simple and power-efficient x86 core for the 32-nm process – in 2011. Limited to SSE2 and SSE3 extensions, it is supposed to consume less than one watt of power. Furthermore, it’s a synthesizable core that can be constituted by a description language for semiconductor devices and can easily be employed in other designs – so AMD is thinking in the direction of system-on-chip (SoC), like Intel with its Atom. The first incarnation is called Ontario: two Bobcat cores and a DirectX-11 graphics core in a BGA package that is meant to be soldered to motherboards for compact “thin and light” notebooks and netbooks; the latter category now officially forms part of AMD’s portfolio.

However, before the new architectures will be cast in silicon, the highly anticipated desktop 6-core processor Thuban, manufactured in the 45-nm process, will be released in 2010. The next step will then be the shrink to 32-nm SOI with the quad-core processor Llano, the first APU with an integrated graphics processor, but presumably still very K10-like CPU cores.

Trouble

While AMD and Intel are really fond of each other now, it seems there was some serious backstage trouble between Intel and Microsoft. For the integrated hypervisor of Windows Server 2008 R2, Microsoft has bravely resorted to a timer function that they themselves had classified as unreliable for former processors: the timer of the Advanced Programmable Interrupt Controller (APIC). Unlike, for example, the CPU timer (Time Stamp Counter, TSC) – which by now is comparatively resistant to power-saving, SpeedStep and turbo-boost modes, but is also virtualised by virtual machines – the APIC timer can also trigger interrupts. Unfortunately, right now, the Nehalem has too many of those, so that the hypervisor falters and then stops, returning the message “Clock_Watchdog_Time-out”.

Intel didn’t specify this bug until September when it was mentioned in its specification updates under AAK119 (Xeon 5500), AAM123 (Xeon 3500), AAO89 (Xeon 3400), AAJ121 (Core i7-900) and AAN87 (Core i7-800, Core i5). And although Microsoft probably indicated the integration of the APIC timer in the new server edition in time, the most recent specification updates from November still include the placating passage: “Intel has not observed this erratum with any commercially available software.“ Microsoft now describes the disaster under error number 975 530, provides a hotfix (on e-mail request) that is not further specified and otherwise proposes the non-serious solution of disabling the power saving states C3 and C6 – which would also shut down the Nehalem’s turbo-boost feature. And it gets worse: the editorial office received a non-published raw version of the error report that even included the brusque “preferred solution” of not using the processors in question. Strong stuff: Microsoft advises against the application of Nehalem processors in servers – so Intel took to the barricades and was able to prevent Microsoft publishing this advice at the very last second.

Translation of the German original from c't 24/09 by Marcel Sieslack

(djwm)