Processor Whispers - About Probabilities and Tunnelling
by Andreas Stiller
New start-ups with interesting new logic technologies draw attention, old companies are on a shopping spree and Intel’s next generation of processors called Sandy Bridge casts a graphical shadow before it.
Once again a small start-up has managed to cause quite a stir in processor circles. The planned GP5 processors from Lyric Semiconductor are supposed to be a thousand times faster at certain tasks than conventional CPUs and, unlike conventional CPUs, they don’t work with binary code, ones and zeros, but with probabilities.
Whereas a traditional processor requires many hundreds of transistors for a simple statistic operation, the Lyric chips are supposed to need no more than a few logic gates to get the job done. The principles of this logic are based on Bayes' theorem, a method of calculating probabilities under certain conditions, formulated in the 18th century by the English mathematician and Presbyterian minister Thomas Bayes. With the introduction of “low power logic for statistical inference” – realised in the usual CMOS process with only three layers – the MIT spin-off went public with its new process at the “International Symposium on Low Power Electronics and Design”.
Unlike their colleagues in the quantum computing faction, who also tend to talk big – for example the Canadian company D-Wave (no news here for a while now) – they already offer a product with good market opportunities: an error corrector for flash memory. According to Lyric, the corrector is 30 times smaller and 10 times more power efficient than conventional technologies. With shrinking structures and even fewer electrons per memory cell, the error ratio of flash chips is increasing dramatically: 1:1000 has already become normal, 1:100 will probably be standard for the next generation, so Lyric’s licensable LEC (Lyric Error Correction) cores may have emerged just in time to better prepare flash technology against the upcoming phase-change, ReRAM and memristor competition. The error ratio is one of the weaknesses of flash memories, which Hewlett-Packard, for instance, intends to attack with the smaller - and, according to HP fellow Stan Williams, less error-prone - memristors.
If all the things that Williams is saying about the memristor - the fourth fundamental passive component next to capacitors, resistors and inductors, which he invented only a few years ago - are true, it will be about three years from now at most before it gets exciting; the first memory to employ this technology will be released around that time.
Meanwhile, Hewlett-Packard has already accomplished something else: it won an entertaining bidding contest for the data storage company 3Par. At first, Dell wanted to buy the Californian company for an unspectacular $1.15 billion. However, out of the blue, Dell was outbid by HP, which offered $1.5 billion. Dell raised the stakes but again HP topped its bid and, after a few more rounds of this game, HP finally emerged as the winner with the final bid of $2.4 billion. HP had also been mentioned as potential buyer of the security software company McAfee, but then Intel announced its bid for McAfee, which came as a surprise to everyone. Intel intends to spend almost $7.7 billion on this acquisition.
Once in the mood, Intel also came to terms with Infineon and bought its wireless-solution branch (WLS) along the way. The deal had been on the table for a long time, but now the German company has contractually agreed to sell its WLS branch at a discount price of $1.4 billion. So, while Intel buys McAfee for almost four times McAfee’s annual turn over, Infineon was apparently unable to get much more than a factor of 1.2 – maybe they gave up too early.
In any case, Intel not only gains a further source for ARM know-how, but also regains a foothold with small Apple devices – where Apple has increasingly been ignoring Intel as a processor manufacturer, a good example being the recently released Apple TV boxes – through the back door of mobile chips. Other former partners, like LG, are also moving away from Intel; a few days ahead of Intel’s developer conference, LG announced that it is going to release a smartphone with NVIDIA’s dual-core ARM processor Tegra 2. In January, at CES, Intel boss Otellini had proudly held up the planned LG smartphone GW900, based on the Atom Moorestown. But it seems LG has now trashed it before the launch, most likely out of frustration over the Intel/Nokia/Meego deal.
At the Hot Chips Conference at the end of August, Intel had been very reluctant to provide details about new architectures because it was waiting - until now - for the Intel Developer Forum (IDF) to present its new prototype Sandy Bridge. And yet, somehow, one specimen and a corresponding board tunnelled through to Anand Lal Shimpi at www.anandtech.com. His test results show that the graphics performance of the chip, slated for the first half of 2011, is better than what it was generally believed Intel would be able to accomplish. With many games, the core i5 2400, with four cores (without HT) with 3.1 and - in turbo mode - 3.4 GHz clock rate, 6 MB L3 cache and probably – Anand wasn't able to confirm this – two graphics cores, performed much better than an AMD Phenom II X4 965 with graphics chip-set (890X) and often outperformed a Radeon HD 5450. The promised performance increase by a factor of two in comparison with Intel’s old graphics chip has been more than accomplished. According to Anand, Intel intends to sell the processor with one as well as with two graphics cores – with six execution units and with twelve execution units respectively.
As for pure computing power, the performance increase of the Sandy Bridge chip is limited. In comparison to an almost equally clocked Core i7 880 - both have two DDR3-1333 memory channels and are specified with 95W TDP - it was generally 10 to 14 percent faster; with DivX 6.5.3 it was a bit slower. But that’s not a surprise: On the one hand, the prototype’s turbo didn’t work and, on the other hand, the new processor runs significantly below its limits. It will only be able to make use of its potential performance advantages once the software supports the 256-bit vector extension AVX. Current Software for 128-bit SSE – as had already been conceded quite a while ago by the developers at the IDF in Shanghai – will be slower than with the exactly fitting SSE units of the predecessors because of the masks needed in the AVX unit. However, it’s very probable that the Sandy Bridge will shine with lots of already AVX-optimised software at the IDF.