IDF: Intel says Moore's Law holds until 2029
Pat Gelsinger, head of the Digital Enterprise Division at Intel, says that Moore's Law will continue to apply for the next few years. In his keynote address at the Intel Developer Forum in Shanghai, he said that the performance of supercomputers would be measured in zettaflops (10 to the 21st power floating-point operations) per second by around 2029. With that power, he said it would be possible to make weather forecasts that would be sufficiently accurate for 14 days. He expects by 2017 it will be possible to create a complete genetic simulation of a cell, which would require an exaflop (10 to the 18th power floating-point operations) per second.
One petaflop (10[sup]15[/sup] power floating-point operations) per second would allow real time analysis of images taken by magnetic resonance scanners. Current systems need around two hours for such analyses. The computer that topped off the Top 500 list in November 2007 (212,992 PowerPC 440 cores clocked at 700MHz) managed 478.2 TFlops/s (trillion flops/s). Intel's fastest system consisting of 3584 quad-core Xeons (65nm Clovertown) clocked at 3GHz, came in third (126.9 TFlops/s) When asked when Intel would reach physical limits, Gelsinger compared Moore's Law to a nightly drive through fog – you can only see around 10 years into the future.
Gelsinger also demonstrated a Dunnington processor with six cores in a Caneland system. Its flex-migration technology allowed him to hot-plug the system to a VMware cluster and move currently operating virtual machines onto it, none of which so much as noticed the switch or the new CPU.
The Nehalem architecture expected this autumn will include a memory controller and the option of an integrated graphics core; Intel wants to use this design to break the petaflop threshold and (using other chips, but the same architecture) build systems that only consume a few (hundred) milliwatts. When discussing this topic, Gelsinger likes to refer to the Chinese fairy tale about the "Monkey King" whose magic wand is scalable from the size of a sewing needle up to a tower. By emphasizing the scalability of a single architecture, Gelsinger has his eye on AMD, which announced in mid-2007 that it would be presenting two different architectures in 2009: one for high-performance processors (Bulldozer), the other for low-power CPUs (Bobcat). A fully operational system with two Nehalem processors and a total of 16 cores was demonstrated recently.
At the end of 2009, the next "tick" step will be the implementation of 32 nm structures. The next "tock" step will follow in 2010, when the Sandy Bridge architecture will provide a whole new array of instruction sets, including a 256-bit SSE unit called AVX (Advanced Vector Extensions) and new three-operand instructions.
Many visitors were interested in the new graphics architecture called Larrabee, but there was little to see of it aside from PR hype. For instance, Intel believes that conventional graphics chips with pipelines will soon (2010) be a thing of the past. Intel expects them to be replaced by such techniques as ray tracing, which will allow games to look as real as photographs. Computing tasks will be spread across a large number of small "Intel Architecture" (IA) cores; Intel's spokespeople do not describe it as x86 because the instruction sets in the upcoming architectures will be greatly expanded and hardly resemble x86. x86 commands will, however, continue to be supported to keep old software running. A new cache architecture that was not described in greater detail is also expected to provide the cores with data. A Vector Instruction Set for floating-point and integer operations feeds the cores. Intel says it will also be providing compilers, optimization tools, and probably even graphics drivers.
More from IDF Shanghai 2008:
- IDF: Intel's atomic era
- Intel developer forum: Shanghai showcase
- IDF: portable devices steal the show