AMD reworks processor roadmap for desktop PCs and notebooks
Compared with the complicated presentation transparencies at last year's Financial Analyst Day, AMD has drastically simplified its processor roadmaps for 2009, 2010 and 2011. It appears that not all the CPU varieties are shown, because the dual core processors AMD is highly likely to continue manufacturing in 2009, are not included in the chart. Deneb, a 45 nm quad core with 4× 512 KBytes of L2 cache and 6 MBytes of L3 cache – that is a total of 8 MBytes of cache – not including the L1 cache – has already been announced by AMD under the name Phenom II X4. The variety that, last year was called Propus, this year it's Propos, also has four cores but no L3 cache, which gives it a total of 2 MBytes of cache. Both CPU versions are likely to be released in the, AM2+ compatible, AM3 housing.
Deneb and Propos are also to be shipped in 2010; this could mean that AMD plans to increase the clock speeds to a value considerably higher than the initially expected maximum of 3 GHz to achieve more profitable prices in its competition with Intel. According to reports by the EETimes, the 45 nm Phenom, which is largely identical to the Shanghai Opteron, occupies 253 square millimetres of chip space, which puts it between a quad core consisting of two Intel Penryn cores – 214 square millimetres – and a Core i7 – 263 square millimetres, although Intel produces these processors on cheaper "bulk silicon" wafers.
The 32 nanometre Orochi processor, with more than four cores, is to supersede the Phenom II X4 in high end desktop PCs only, in 2011. In the same year, AMD also plans to release the first Fusion combo processors, initially announced for "2008 at the earliest". These processors combine the CPU and GPU cores on one chip, or in system-on-chip technology in one housing. For the time being, Fusion will therefore remain the name of a concept that also includes "balanced" PC platforms with discrete components or chipset graphics. This could mean that Intel's system-on-chip solutions – Havendale/Auburndale – might become available considerably earlier than the combo processors code-named Llano – 4 cores plus GPU for desktop PCs and powerful notebooks – and Ontario – 2 cores plus GPU for lean mobile computers and mini notebooks – announced by AMD.
For notebooks, AMD plans to introduce two new processors each in 2009 and 2010. Caspian seems to be a simple 45 nm "shrink" of the current Turion Ultra – Griffin – and will be released with the Tigris platform in the second half of 2009. Conesus is still built in 65 nm technology, but said to require a TDP of only less than 25 Watts. It sits in a Ball Grid Array (BGA) housing that can directly be soldered onto the motherboards of particularly compact notebooks. This platform, called Yukon, is expected to ship in the first half of 2009.
2010 will be the year for AMD's first mobile quad core – Champlain – while the more economical BGA chips will be continued with Geneva; both platforms are to offer DDR3 SDRAM. The already mentioned Ontario successor with 32 nm structures in a BGA housing is planned for 2011.
The announcement that the combo processors will only be integrated into the 32 nm generation of chips in 2011 adds weight to earlier speculations that these processors are to be manufactured, not by contract suppliers like TSMC or UMC, but by AMD itself – and, according to the speculation, by AMD's by then split off manufacturing branch and possibly on cheaper "bulk silicon" instead of SOI wafers. The CPU cores in the Llano and Ontario are then to be part of the Bulldozer generation – another piece of information that fits in with earlier speculations. It remains unclear whether AMD will incorporate the SSE5 instruction set extension it announced long ago, or whether it will rather go with Intel's Advanced Vector Extensions (AVX) set to have its debut with Sandy Bridge in 2011. AMD needs to renegotiate its cross licensing agreement with Intel by 2011, which will have an impact on the choice between SSE5 and AVX. Intel's forthcoming Ct compiler (C for Throughput Computing) is to incorporate Larrabee graphics chips as coprocessors and later use AVX processors.